Named networks, rats nest, deliberate netlist changes + back annotationĭraw using netlist/footprints imported from schematicsĪlternatively create netlist from scratch while drawing the PCB Holes, slots, blind/buried vias, different shape on different layers (including non-copper layers), arbitrary polygon shapeĪny object and layer supported in footprint rich metadata option for run-time generated footprints TEDAx netlist, gEDA/gaf sch, gEDA/gaf netlist, EasyEDA netlist, dsn, edif, ipcd356, HP-GL, tEDAx, PADS ASCII netlist, Orcad netlist, Accel EDA netlist, Protel netlist 2.0Ĭopper, silk, mask, paste, plated route/cut, unplated route/cut, arbitrary documentation/misc layers
Lihata (native), tEDAx footprint, KiCad s-expression modules, geda/PCB's. pcb, Eagle (binary and xml, read-only), Protel/Autotrax (read-only), Protel 98/99 (read-only), Altium (read-only), Mentor Graphics Hyperlynx Lihata (native), tEDAx board, KiCad's s-expr kicad_pcb, geda/PCB's. Lihata (structured text tree) support for loading and saving all old file versions Multiple layers (16 copper, compile time tunable limit)Įditable solder mask, paste, assembly, keepout, documentation drawingsīoard size up to 2x2 meter at nanometer precision Pcb-rnd - datasheet Main News Doc & FAQ & pool & tutorials Support People Events & timeline pcb-rnd pcb-rnd - datasheet layout characteristics
0 kommentar(er)
